1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of fabricating the same. More particularly, the present invention relates to a semiconductor memory device having a multiple tunnel junction pattern and a method of fabricating the same.
2. Description of the Related Art
Advantages of dynamic random access memory (DRAM) include higher integration in a limited area than a memory device, such as static random access memory (SRAM), and faster operation speed than a memory device, such as a flash memory. A disadvantage of DRAM, however, is that it must be refreshed periodically in order to retain stored data. Thus, the DRAM consumes power even in a stand-by mode.
On the contrary, a non-volatile memory device such as a flash memory device has the advantage that periodic refreshes are unnecessary. The non-volatile memory device, however, has several disadvantages such as a high voltage demand for programming or erasing memory cells and slow operation speed in comparison with a DRAM or an SRAM. Thus, a new memory device uniting DRAM with flash memory has been developed.
FIG. 1 illustrates a diagram showing a unit cell of a semiconductor memory device having a conventional multiple tunnel junction pattern.
Referring to FIG. 1, a unit cell of a semiconductor memory device includes a planar transistor and a vertical transistor. The planar transistor is formed at a predetermined region of a semiconductor substrate 100, and includes a drain region 124d, a source region 124s and a floating gate 104. The drain region 124d and the source region 124s are spaced apart from each other. The floating gate 104 is arranged on a channel region between the drain region 124d and the source region 124s. The drain region 124d corresponds to a bit line and the floating gate 104 corresponds to a storage node. A gate insulating layer 102 is interposed between the storage node 104 and the channel region.
A multiple tunnel junction pattern 110 and a data line 122 are sequentially stacked on the storage node 104. The multiple tunnel junction pattern 110 includes semiconductor layers 106 and tunnel insulating layers 108, which are alternately and repeatedly stacked. An utmost top layer of the multiple tunnel junction pattern 110 may be either the semiconductor layer 106 or the tunnel insulating layer 108. The data line 122 is extended to be electrically connected with a plurality of adjacent memory cells. A gate interlayer dielectric layer 126 covers sidewalls of the multiple tunnel junction pattern 110 and the data line 122. The gate interlayer dielectric layer 126 also covers the data line 122.
A word line 128 is arranged on the gate interlayer dielectric layer 126 to cross over the data line 122. The word line 128 overlaps with the storage node 104 and the multiple tunnel junction pattern 110. The data line 122, the multiple tunnel junction pattern 110, the storage node 104 and the word line 128 form the vertical transistor. The data line 122 corresponds to a drain of the vertical transistor, and the storage node 104 corresponds to a source of the vertical transistor.
FIG. 2A illustrates an energy band diagram of a conventional semiconductor memory device, taken along line I-Ixe2x80x2 of FIG. 1.
FIG. 2B illustrates an energy band diagram of a conventional semiconductor memory device, taken along line II-IIxe2x80x2 of FIG. 1.
Referring to FIGS. 2A and 2B, the multiple tunnel junction pattern 110 of FIG. 1 has a plurality of high potential barriers provided by the tunnel insulating pattern 108. Generally, the semiconductor layer 106 is formed of an undoped silicon layer, and the word line 128 and the storage node 104 are formed of a P-type silicon layer and an N-type silicon layer, respectively. As illustrated in FIG. 2A, an accumulation layer is formed on sidewalls of the semiconductor layer 106 by an influence of the P-type word line 128. Therefore, the tunnel insulating pattern 108 adjacent to the gate dielectric layer 126 to a predetermined distance forms a relatively high potential barrier. As a result, in the stand-by mode, charges may leak out through a central region of the tunnel insulating pattern 108 having a relatively low potential barrier.
It is a feature of an embodiment of the present invention to provide a semiconductor memory device having a structure such that charge leakage through a multiple tunnel junction pattern may be significantly decreased and a method of fabricating the same.
It is another feature of an embodiment of the present invention to provide a semiconductor memory device having a decreased charge leakage and a high coupling ratio and a method of fabricating the same.
It is still another feature of an embodiment of the present invention to provide a semiconductor memory device having a superior read operation at a low read voltage and a method of fabricating the same.
In order to provide these and other features, an embodiment of the present invention is directed to a semiconductor memory device having a multiple tunnel junction pattern, wherein a cell of the semiconductor memory device includes a planar transistor and a vertical transistor. The planar transistor is arranged at a predetermined region of a semiconductor substrate, and includes a first and a second conductive region""that are spaced apart from and parallel to each other, and a storage node arranged on a channel region between the first and the second conductive region. The vertical transistor includes the storage node, a multiple tunnel junction pattern arranged on the storage node, a data line crossing over the multiple tunnel junction pattern and parallel to the first and the second conductive region, and a word line crossing over the data line and covering both sidewalls of the multiple tunnel junction pattern and both sidewalls of the storage node. In a cross-sectional view taken along the word line, a width of the multiple tunnel junction pattern is narrower than a width of the storage node and a width of the data line. That is, the multiple tunnel junction pattern has a narrow width in a limited area. Thus, a leakage current flowing through a central region of the multiple tunnel junction pattern may be decreased.
Preferably, the multiple tunnel junction pattern may be formed by alternately and repeatedly stacking semiconductor patterns and tunnel insulating patterns. The semiconductor pattern is preferably formed of a material having a faster etch rate and thermal oxidizing rate than the storage node layer.
A gate insulating layer may be interposed between the storage node and the channel region. A gate interlayer dielectric layer may be interposed between the word line and the multiple tunnel junction pattern, and between the word line and the storage node. The storage node corresponds to a gate electrode of the planar transistor and simultaneously corresponds to a source of the vertical transistor. Thus, since the storage node protrudes from both sidewalls of the multiple tunnel junction pattern, capacitance between the word line and the storage node may be maximized. A capping insulating pattern may be interposed between the word line and the data line.
In another embodiment of the present invention, a semiconductor memory device includes a plurality of conductive regions parallel to a semiconductor substrate; a plurality of storage nodes arranged on the semiconductor substrate between the conductive regions; trench regions formed at the semiconductor substrate between the storage nodes arranged on a line parallel to the conductive regions; a plurality of multiple tunnel junction patterns stacked on the storage nodes; isolation layers for filling the trench regions; a plurality of data lines arranged between the conductive regions for covering the multiple tunnel junction patterns and the isolation layers therebetween; and a plurality of parallel word lines for crossing over the data lines, wherein a width of the multiple tunnel junction pattern is narrower than widths of the data line and the storage node in a cross-sectional view taken along the word line, and the word lines for covering sidewalls of the storage nodes and the multiple tunnel junction patterns.
A method of forming the semiconductor memory device according to an embodiment of the present invention, includes forming a plurality of trench regions two-dimensionally arranged at a predetermined region of a semiconductor substrate along a row direction and a column direction, to define a mesh-shaped active region, and simultaneously sequentially stacking a gate insulating layer, a storage node layer and a multiple tunnel junction layer on the mesh-shaped active region, the multiple tunnel junction layer including semiconductor layers and tunnel insulating layers that are alternately and repeatedly stacked, and the semiconductor layer formed of a material having a faster etch rate or thermal oxidizing rate than the storage node layer; forming a plurality of island-shaped isolation patterns to fill the trench regions; forming an interconnection layer on an entire surface of the resultant structure where the isolation patterns are formed; continuously patterning the interconnection layer, the multiple tunnel junction layer, the storage node layer and the gate insulating layer to form a plurality of data lines parallel to the column direction and simultaneously sequentially stacking a gate insulating pattern, a storage node pattern and a multiple tunnel junction pattern in regions between the isolation layers under the data lines, wherein a width of the multiple tunnel junction pattern is narrower than widths of the storage node pattern and the data line in a cross-sectional view taken along the row direction; forming a conformal gate interlayer dielectric layer on an entire surface of the resultant structure having the storage node pattern; and forming a plurality of parallel word lines for crossing over the data lines on the gate interlayer dielectric layer. The storage node layer may be formed of a silicon layer and the semiconductor layer may be formed of a silicon germanium layer (SiGe).
After forming the storage node, conductive regions may be formed at a semiconductor substrate located at both sides of the storage node by implanting impurities therein.